1. Field of the Invention
The present invention relates to the memory controller and, more particularly, to a memory controller capable of estimating memory power consumption.
2. Description of Related Art
Currently, with rapidly developing semiconductor process, embedded system design has entered into an era of System-on-Chip (SOC) which integrates a CPU module, specific IPs and peripherals into a single chip as an application specific system. FIG. 1 is a block diagram of an MPEG II SOC decoding system. As shown, to increase operation speed, an on-chip memory module 120 is typically added into the SOC system and also data cache and instruction cache are added into the MIPS (millions of instructions per second) module 110 (not shown). However, the on-chip memory module 120, data cache and instruction cache are limited by process so as to have only 8 Kbyte, 16 Kbyte or 32 Kbyte typically.
Obviously, the aforementioned on-chip memory module 120 cannot meet with required memory for such a typical SOC system. In addition, due to limited die size, large amount of memory cannot be implemented in the SOC system. Thus, to meet with required memory, in addition to the MPEG II SOC decoding system, a synchronous DRAM 180 is added to allow the MIPS module 110 to store temporary data. However, power consumption cannot be estimated because the synchronous DRAM 180 is implemented outside the SOC system. One approach to estimate the power consumption applies average power recorded in datasheet for the synchronous DRAM 180 to power consumption estimation, but it is unable to perform a precise estimation. Therefore, it is desirable to provide an improved power estimation to mitigate and/or obviate the aforementioned problems.